1. Technical Field
The present invention relates to a self-refresh control circuit and a semiconductor device having this circuit.
2. Related Art
In the semiconductor device having a DRAM (Dynamic Random Access Memory) cell, to hold data stored in a DRAM cell, a refresh operation that holds an electric charge accumulated every constant cycle is required to be performed. Hence, the semiconductor device is provided with a self-refresh control circuit so as to perform a refresh operation of the DRAM cell every constant cycle without having an access to the semiconductor apparatus from the outside.
A cause of data disappearance of the DRAM cell is mainly an electric charge disappearance due to leak current having temperature dependency of the device. Incidentally, in the low to the normal temperature state of the device, an amount of disappearance of the electric charge is small, and in the high temperature state, an amount of disappearance of the electric charge is large. Hence, in the low to the normal temperature state of the device, even when the cycle of performing the refresh operation is long, the data can be held, while in a high temperature state, the electric charge easily disappears, and therefore, the cycle of the refresh operation is required to be set short.
Patent Document 1, which is Japanese Patent Laid-Open No. 2006-031830, shows a self-refresh control circuit that generates refresh cycles different for the normal temperature and the high temperature. FIG. 22 is a functional block diagram showing the configuration of a conventional self-refresh control circuit disclosed in Patent Document 1. This refresh control circuit is configured to include a constant current generating circuit 220, a constant current generating circuit 221, a bias voltage adjusting circuit 222, a ring oscillator 223, a counter circuit 224, and a refresh row-address generating circuit 225. The constant current generating circuit 220 hardly depends upon the temperature of the device, and generates the constant voltage BIAST. The constant current generating circuit 221 has temperature dependency, and generates a constant voltage BIASN according to the temperature.
The bias voltage adjusting circuit 222 generates a bias voltage BIASS according to bias voltages BIAST and BIASN, and outputs the bias voltage BIASS to a ring oscillator 223. The ring oscillator 223 generates a pulse signal PHYO whose cycle changes according to the inputted bias voltage BIASS. The counter circuit 224 counts the pulse signal PHYO, and outputs an activation signal PHYS when the predetermined number of times is exceeded. The refresh row-address generating circuit 225, according to this activation signal PHYS, switches over the row-address that performs the refresh operation. In this manner, by providing the constant current generating circuit 220 small in temperature dependency and the constant current generating circuit 221 large in temperature dependency, the refresh cycle having cycles different for the normal temperature and the high temperature can be provided.
FIG. 23 is a circuit diagram showing the configuration of the bias voltage adjusting circuit 222 possessed by a self-refresh control circuit according to Patent Document 1. The bias voltage adjusting circuit 222 is configured to include P-channel transistors P7 and P8 and N-channel transistors N8 to N10. The P-channel transistor P7 has its source connected to a power source VDD and its drain and gate connected to a node ND6. The P-channel transistor P8 has its source connected to the power source VDD and its drain connected to a node ND7, and its gate connected to the node ND6. The N-channel transistor N8 has its source grounded, its drain connected to the node ND6, and its gate inputted with the bias voltage BIAST. The N-channel transistor N9 has its source grounded, its drain connected to the node ND6, and its gate inputted with the bias voltage BIASN. The N-channel transistor N10 has its source grounded, its drain and gate connected to the node ND7. In the bias voltage adjusting circuit 222, the voltage of the node ND7 is outputted as the bias voltage BIASS.
Patent Document 2, which is Japanese Patent Laid-Open No. 2006-031860, discloses a self-refresh control circuit that changes a refresh cycle in stages according to the temperature. FIG. 24 is a functional block diagram showing a configuration of a conventional self-refresh control circuit shown in Patent Document 2. This self-refresh control circuit is configured to include a band gap type reference potential generating circuit 231, a current control bias circuit 232, a comparison voltage generating circuit 233, a ring oscillator 234, a frequency divider circuit 235, a frequency selecting circuit 236, and a temperature detector 237. The band gap type reference potential generating circuit 231, the current control bias circuit 232, the comparison voltage generating circuit 233, and the ring oscillator 234 are configured to generate a pulse signal having a cycle according to the temperature of the device. The frequency divider circuit 235 inputs this generated pulse signal, and outputs signals of plural divided frequencies. The frequency selecting circuit 236 outputs refresh reference signals REFRQ corresponding to the plural pieces of the divided frequencies generated by the frequency divider circuit 235 according to the signal inputted from the temperature detector 237. In this manner, by selecting the signals of the divided frequencies according to the temperature of the device, the refresh cycle can be changed in steps according to the temperature.
FIG. 25 is a circuit diagram showing a part of the configuration of the current control bias circuit 232 of the self-refresh control circuit disclosed in Patent Document 2. The current control bias circuit 232 is configured to include the P-channel transistors QP07 to 10 and the N-channel transistors QN05 to 09. The P-channel transistor QP07 has its source connected to a current source ISO1, and its drain connected to a node NO1, and its gate inputted with a control voltage VBE. The P-channel transistor QPO8 has its source connected to the current source ISO1, its drain connected to a node NO2, and its gate inputted with a control voltage VRTRO. The N-channel transistor QN05 has its source grounded, and its drain connected to the node NO1, and its gate connected to the node NO2. The N-channel transistor QN06 has its source grounded, and its drain and gate connected to the node NO2. The N-channel transistor QN07 has its source grounded, and its drain and gate connected to the node NO2. The N-channel transistor QN08 has its source grounded, and its drain connected to the current source ISO2, and its gate connected to the node NO2. The P-channel transistor QN09 has its source connected to the power source VDD, and its drain connected to the drain of the N-channel transistor QN08, and its gate connected to the current source ISO2. The P-channel transistor QP10 has its source connected to the power source VDD, and its drain connected to the drain of the N-channel transistor QN09, and its gate connected to a control voltage OSCBP. The N-channel transistor QN09 has its source grounded, and its drain connected to the drain of the P-channel transistor QP10, and its gate connected to a control voltage OSCBN.
In the self-refresh control circuit disclosed in Patent Document 1, when the temperature decreases, the bias voltage BIASN is grounded, so that the bias voltage adjusting circuit 222 outputs a constant voltage decided by the bias voltage BIAST. However, in the self-refresh control circuit disclosed in Patent Document 1, no means is provided for measuring and adjusting the bias voltage BIAST only, and the fluctuation of the bias voltage BIAST due to the fluctuation of the process and the like cannot be compensated. As a result, the bias voltage BIAST at the normal temperature cannot be set to a desired value, and to perform a guarantee of proper operation, the refresh cycle must be set short in consideration of the fluctuation of the process. Hence, a problem arises that the standby current at the normal temperature is increased by an amount corresponding to shortening of the refresh cycle.
Further, in the self-refresh control circuit disclosed in Patent Document 2, in the circuit diagram shown in FIG. 25, when the temperature decreases and a potential of the node NO1 of the current control bias circuit 232 decreases so that the N-channel transistor QN08 is cut off, the potentials of the control voltages QSCBP and QSCBN output a constant voltage decided by the current source ISO2. Incidentally, the current source ISO2 is considered to be equivalent to a resistor in a constant bias condition. However, in the self-refresh control circuit disclosed in Patent Document 2, since there is no means available for measuring and adjusting the control voltages QSCBP and QSCBN only, at the normal temperature, when the current source ISO2 does not become a desired resistance due to the fluctuation of the device, a fluctuation occurs in the refresh cycle at the normal temperature. Further, when the detection temperature of the temperature detector 237 does not become a desired value due to the fluctuation of the device, a fluctuation further occurs in the refresh cycle at the normal temperature. Hence, when the refresh cycle is designed to be short in consideration of these fluctuations, a problem arises that the standby current increases at the normal temperature similarly to Patent Document 1.
Usually, the DRAM mounted with the self-refresh control circuit is, for example, mounted on a mobile-phone terminal and the like. Since the mobile-phone terminal is almost used at the normal temperature, the reduction of a consumption power of the standby current at such normal temperature time becomes a key question.